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Industry’s First Mobile Phone Application Processor with Parallel Processing

4th October , 2004

ASIA : NEC introduced the MP211, the industry’s first application processor for mobile phones with three internal CPU cores. The new product leverages NEC Electronics’ parallel processing and low power consumption technologies, enabling high performance multimedia processing such as terrestrial digital broadcast reception, videophone, and music playback while maintaining low power consumption.

Main Features of the MP211

Three ARM CPU cores and new software enable optimized processing for multiple mobile phone applications and offer higher performance. Compatibility with software previously used with single-CPU application processors minimizes development time.

Linux OS platform offers greater flexibility and efficiency in software development, allowing development using open source software.

Includes NEC Electronics’ proven digital signal processor (DSP), with industry-leading sales of more than 160 million units in Japan, which allows optimal processing of multimedia applications via software. With this DSP, high performance applications such as terrestrial digital broadcast reception and videophone functions can be operated without accessing the hardware.

New bus architecture allows the three CPU cores and the DSP to share just one memory unit, simplifying circuitry around the memory chip and enabling high speed data transfer, leading to improved performance compared to previous single-CPU architectures.

Combination of above-mentioned multi-CPU and DSP technologies, together with low power consumption technologies, reduces power consumption by approximately 30 percent (for terrestrial digital broadcast reception and videophone operations, compared with single-CPU application processors).

“Parallel processing technology is a key to enabling enhancement of future applications, especially those that require both high performance and low power consumption,” stated Yoshiharu Tamura, General Manager, Mobile Terminal Unit, NEC Corporation. “With the addition of the Linux operating system, we can expect greater usability and more efficient development.”
Recently, mobile phone requirements have shifted dramatically from traditional functions such as standard calling and camera features, toward feature-rich functions such as videophone, animation and games, music playback, e-money, navigation systems, and terrestrial digital broadcast reception. In coming years, an even greater array of services is expected.
With these changes, hardware and software development for mobile phones has become increasingly complex, requiring greater resources. For mobile phone developers, it is critical to solution that simultaneously enables both high performance and low power consumption, while minimizing development time by ensuring backward compatibility with existing application software.
However, adding high performance functions such as image and audio processing to current single-CPU application processors results in higher CPU operating frequencies, which leads to higher power consumption and ultimately reduced talk time and standby time.
The MP211 application processor solves this dilemma by simultaneously providing higher performance and lower power consumption, and will be an integral part of NEC Electronics’ lineup of solutions for the mobile phone space. NEC Electronics will demonstrate the MP211, as well as other new products, at CEATEC Japan 2004, beginning October 5th at Makuhari Messe.

Availability
The application processor will be available in combination with DDR SDRAM in a stacked System in Package (SiP) format, ideal for the small geometries of mobile phones. Samples will be available starting in January 2005. Volume production is expected to begin in the first half of 2005, with monthly production to reach 1 million units by 2007. Availability is subject to change.

MP211 Specifications
CPUs: three ARM926EJ-S cores
Operating frequency: 200MHz (max.)
Instruction cache: 16KB per CPU
Data cache: 16KB per CPU

DSP: NEC Electronics DSP core
Operating frequency: 200MHz (max.)
Instruction cache: 16KB
Instruction RAM: 64KB
Data RAM: 64KB

640KB on-chip memory (can be used as workspace for LCD frame buffer)

Other specifications:
-Memory interface (DDR SDRAM, flash memory, asynchronous memory)
-1seg terrestrial digital broadcast reception OFDM interface
-LCD interface, camera interface, ITU-R BT.656 interface
-Security accelerator, 2D/3D graphics accelerator
-Image processor supporting image enlargement/reduction/blending/rotation
-Baseband LSI serial interface, voice/audio serial interface
-USB OTG
-Timer, external interruption, GPIO, UART, I2C, MICROWIRE™
-Memory card interface

Manufacturing process: 0.13µm CMOS process
I/O power supply: 1.8V
Internal power supply: 1.0-1.2V (during operation), 0.7V (CPU data retention)
Package: 377-pin FPBGA, 64MB DDR SDRAM System in Package (SiP)

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