Cost Savings For 3G Base Station Manufacturers

22nd March , 2004

US : Analog Devices extended its VersaCOMM® family of digital up- and down-converters. Among the new products is the AD6633, a digital up-converter featuring breakthrough technology that significantly reduces output power requirements for 3G wireless base station power amplifiers (PA).

The AD6633’s innovative VersaCREST™ crest reduction engine enables optimum baseband-to-IF (intermediate frequency) signal conversion by anticipating and reducing power peaks earlier in the signal chain. Traditionally, base station manufacturers have relied on expensive, highly linear power amplifiers to avoid output signal distortion caused by large peaking signals. Analog Devices' new solution reduces peak-to-average power by up to 6 dB, the equivalent of replacing a 40 W amplifier with a 10 W amplifier. This means that manufacturers can either reduce their power amplifier expense while achieving dramatic power savings of up to 75 percent, or, using the existing 40 W PA, an operator can support up to four times the coverage area.

The AD6633 is Analog Devices' first digital up-converter with crest factor reduction technology for CDMA2000, W-CDMA, and TD-SCDMA, 3G wireless transmitter applications. Operating at 125 MSPS and processing four or six channels, the AD6633 is capable of trading crest factor reduction against signal distortion. The signal distortions can be allocated dynamically to any individual channel; thus, allowing operators to configure performance preferences for high quality data or lower quality voice communications. The converter also features programmable wideband channel filters that can be implemented for CDMA2000, W-CDMA, or TD-SCDMA standards, enabling manufacturers to use a single device across multiple platforms.

“As demand for 3G services accelerates, wireless infrastructure manufacturers and assembly contractors will be seeking effective design solutions that reduce their starting capital and operational costs,” said Kevin Kattmann, product line director for high-speed converters, Analog Devices. “The AD6633's innovative VersaCREST™ crest reduction engine delivers unparalleled signal conditioning performance in peak-to-average power reduction and reduces the power amplifier cost component within base station designs—a winning combination for both our customers and their subscribers.”

More About the AD6633 Digital Up-Converter
The AD6633 wideband transmit signal processor operates on up to six-channels with user configurability and speeds of 125 MSPS. Its VersaCREST™ crest reduction engine reduces demands on external power amplifiers. It features one 20-bit input port, shared among six processing channels, with 18-bit parallel output ports. Filters include: all-pass phase equalizer filters for CDMA2000, programmable RAM coefficient FIR filters with re-sampling, FIR interpolating filters (two per channel), complex FIR filters with frequency equalization and fifth-order interpolating CIC filters (one per channel). It offers full complex NCO for 32-bit tuning fine resolution, worst spur better than –105dBc, and output automatic gain control. The AD6633 requires 3.3V input/output and 1.8V core supplies. In addition to 3G wireless infrastructure applications, the AD6633 is also suitable for general-purpose communications applications where power crests and system costs present design challenges.

A New Digital Down-Converter
Analog Devices also introduced today a new wideband digital down-converter for multi-carrier receivers. The AD6636 wideband digital down-converter is capable of processing up to six UMTS, CDMA2000, or TD/SCDMA channels at speeds of up to 150 MSPS. Each channel is dynamically reconfigurable, operates independently, and includes cascaded signal-processing elements: a frequency translator, programmable decimating filter, and automatic gain control (AGC) circuitry that optimizes the dynamic range of the system. The receiver input block allows routing of the ADC data to any or all of the six receive processing channels.

The AD6636 features a fractional clock multiplier that uses the ADC clock to produce a digital down converter master clock up to 200 MHz. This internal phased-locked loop (PLL) allows optimum digital clock rates, regardless of the converter sampling rate, enabling the best possible digital signal decimation and filtering. Two 16-bit parallel output ports accommodate high data rate 3G applications. An on-chip interpolating half band filter can also be used to further increase the output rate while still allowing for very efficient filters. In addition, each parallel output port has a digital AGC for output data scaling.

More About ADI’s Transceiver Signal Chain
The AD6633 up converts baseband data from the digital signal processor (DSP) to a digital IF. This coupled with Analog Devices AD9777 TxDAC+®, and AD8349 direct RF up-converter offers a complete, highly programmable transmit signal chain. On the receive side this is complemented by the AD8343 high IP3 active mixer and the AD6654 MxFETM wideband IF-to-baseband converter. Rounding out this complete signal chain portfolio for wireless infrastructure is the high-performance TigerSHARC® Processor. Achieving 4.8 billion multiply accumulates per second (GMACS) and 3.6 billion floating-point operations per second (GFLOPS) at 600 MHz, the TigerSHARC® ADSP-TS201 can support full software radio implementations in 3G wireless base stations.

Pricing and Availability
The AD6633 and AD6636 are sampling now and will be available in production quantities in August 2004. They are available in 196-lead BGA (ball grid array) packages. The AD6633 is priced at $60.00 per unit in 10,000-piece quantities for the six-channel version and at $40.00 per unit in 10,000-piece quantities for the four-channel version. The AD6636 is priced at $43.50 per unit in 10,000-piece quantities for the six-channel version and at $29.00 per unit in 10,000-piece quantities for the four-channel version.

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